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1014 HD66520T (160-channel 4-level grayscale display column driver with internal bit-map ram) description the hd66520 is a column driver for liquid crystal dot-matrix graphic display systems. this lsi incorporates 160 liquid crystal drive circuits and a 160 240 2-bit bit-map ram, which is suitable for lcds in portable information devices. it also includes a general-purpose sram interface so that draw access can be easily implemented from a general-purpose cpu. the hd66520 also has a new arbitration method which prevents flicker when the cpu performs draw access asynchronously. the on-chip display ram greatly decreases power consumption compared to previous liquid crystal display systems because there is no need for high-speed data transfer. the chip also incorporates a four-level grayscale controller for enhanced graphics capabilities, such as icons on a screen. features duty cycle: 1/64 to 1/240 liquid crystal drive circuits: 160 low-voltage logic circuit: 3.0 to 5.5-v operation power supply voltage high-voltage liquid crystal drive circuit: 8 to 28-v liquid crystal drive voltage grayscale display: frc four-level grayscale display grayscale memory management: packed pixel internal bit-map display ram: 76800 bits (160 240 lines two planes) cpu interface ? sram interface ? address bus: 16 bits, data bus: 8 bits
HD66520T 1015 high-speed draw function: supports burst transfer mode arbitration function: implemented internally (draw access has priority) access time ? 180 ns (v cc = 5v operation) ? 240 ns (v cc = 3v operation) low power consumption: v cc = 3.3-v operation ? 360 a during display (logic circuit, liquid crystal drive circuit) ? 10 ma during ram access (logic circuit) v cc = 5.5-v operation ? 400 a during display (logic circuit, liquid crystal drive circuit) ? 16 ma during ram access (logic circuit) on-chip address management function refresh unnecessary internal display off function package: 208-pin tcp ordering information type no. tcp outer lead pitch (m) HD66520Ta0 straight tcp 200 HD66520Tb0 folding tcp 200
HD66520T 1016 pin arrangement v2l v4l v3l v1l v ee1 v cc1 ls0 ls1 shl gnd1 flm m cl1 dispoff cs we oe a0 a1 a2 a3 a4 a5 a6 a7 a8 a9 a10 a11 a12 a13 a14 a15 gnd2 db0 db1 db2 db3 db4 db5 db6 db7 v cc2 v ee2 v1r v3r v4r v2r 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 160 159 158 157 156 155 154 153 152 151 y160 y159 y158 y157 y156 y155 y154 y153 y152 y151 10 9 8 7 6 5 4 3 2 1 y10 y9 y8 y7 y6 y5 y4 y3 y2 y1 top view note : this figure does not specify the tcp dimensions.
HD66520T 1017 pin description classi- fication symbol pin no. pin name i/o number of pins function power supply v cc1 v cc2 v cc v cc v cc Cgnd: logic power supply gnd1 gnd2 gnd gnd v ee1 v ee2 lcd drive circuit power supply v cc Cv ee : lcd drive circuit power supply v1l, v1r lcd select high-level voltage input 2 lcd drive level power supplies see figure 1. the user should apply the same v2l, v2r lcd select low-level voltage input 2 potential to the l and r side. v3l, v3r lcd deselect high-level voltage input 2 v4l, v4r lcd deselect low- level voltage input 2 control ls0, ls1 lsi id select switch pin0 and 1 input 2 pins for setting lsi id no (refer to signals pin functions for details). shl shift direction control signal input 1 reverses the relationship between lcd drive output pins y and addresses. flm first line marker input 1 first line select signal. cl1 data transfer clock input 1 clock signal to transfer the line data to an lcd display driver block. m ac switching signal input 1 switching signal to convert lcd drive output to ac. ',632) ) display off signal input 1 control signal to fix lcd driver outputs to lcd select high level. when low, lcd drive outputs y1 to y160 are set to v1, or lcd select high level. display can be turned off by setting a common driver to v1.
HD66520T 1018 classi- fication symbol pin no. pin name i/o number of pins function bus interface a0 to a15 address input input 16 upper 9 bits (a15Ca7) are used for the duty-directional addresses, and lower 7 bits (a6Ca0) for the output-pin directional addresses (refer to pin functions for details). db0 to db7 data input/ output i/o 8 packed-pixel 2-bit/pixel display data transfer (refer to pin functions for details). &6 chip select signal input 1 lsi select signal during draw access (refer to pin functions for details). :( write signal input 1 write-enable signal during draw access (refer to pin functions for details). 2( output enable signal input 1 output-enable signal during draw access (refer to pin functions for details). lcd drive output y1 to y160 lcd drive output output 160 each y outputs one of the four voltage levels v1, v2, v3, or v4, depending on the combination of the m signal and data levels note: the number of input outer leads: 48 v1 v3 v4 v2 figure 1 lcd drive levels
HD66520T 1019 pin functions control signals ls0 and ls1 (input): the ls pins can assign four (0 to 3) id numbers to four lsis, thus making it possible to connect a maximum of four hd66520s sharing the same &6 pin to the same bus (figure 2.) shl (input): this pin reverses the relationship between lcd drive output pins y1 to y160 and addresses. there is no need to change the address assignment for the display regardless of whether the hd66520 is mounted from the back or the front of the lcd panel. refer to driver layout and address management for details. flm (input): when the pin is high, it resets the display line counter, returns the display line to the start line, and synchronizes common signals with frame timing. cl1 (input): at each falling edge of data-transfer clock pulses input to this pin, the latch circuits latch display data and output it to the liquid crystal display driver section. m (input): ac voltage needs to be applied to liquid crystals to prevent deterioration due to dc voltage application. the m pin is a switch signal for liquid crystal drive voltage and determines the ac cycle. ',632)) ',632)) (input): a control signal to fix liquid crystal driver output to liquid crystal select high level. when this pin is low, liquid crystal drive outputs y1 to y160 are set to liquid crystal select high level v1. the display can be turned off by setting the outputs of the common driver to level v1. in this case, display ram data will be retained. therefore, if signal ',632)) returns to high level, liquid crystal drive outputs will return to normal display state. draw access can be executed when signal ',632)) is either in high or low state. hd66520 hd66520 id = 0 id = 2 hd66520 hd66520 id = 1 id = 3 hd66503 hd66503 480 lcd panel ls1 l l h h l: low level h: high level ls0 l h l h id no. 0 1 2 3 ram address arrangement upper-left of lcd panel lower-left of lcd panel upper-right of lcd panel lower-right of lcd panel 320 figure 2 ls pins and address assignment
HD66520T 1020 power supply pins v cc 1 C 2 and gnd1C2: these pins supply power to the logic circuit. v cc 1 C 2 and v ee 1 C 2 : these pins supply power to the liquid crystal circuits. v1l, v1r, v2l, v2r, v3l, v3r, v4l, v4r: these pins are used to input the level power supply to drive the liquid crystal. bus interface &6 &6 (input): a basic signal of the ram area. when &6 is low (active), the system can access the on-chip ram of the lsi whose address space, set by ls0, ls1, and shl pins, contains the input address. when &6 is high, it is prohibited to access the ram. in addition, this signal is used for arbitration control when draw access from the cpu competes with display access that is used to transfer line data to the liquid crystal panel. note that there are restraints for the pulse width, as shown in figure 3. the example shown here is when v cc = 3v for a write operation. a0 to a15 (input): a bus to transfer addresses during ram access. upper nine bits (a15 to a7) are duty-direction addresses, and lower seven bits (a6 to a0) are output pin-direction addresses. :( :( (input): when :( is during low level, the ram is in active mode, and during high level, it is prohibited to access the ram. this is used to write display data to the ram. only the lsi whose address space, set by pins ls0, ls1, and shl, contains the input address can be written to when &6 is low. 2( 2( (input): when 2( is during low level the ram is in active mode, and during high level, it is prohibited to access the ram. this is used to read display data from the ram. only the lsi whose address space, set by pins ls0, ls1, and shl, contains the input address can be read from when &6 is low. db0 to db7 (input/output): the pins function as data input/output pins. they can accommodate to a data format with 2 bits/pixel, which implement packed-pixel four-level grayscale display. t fs t clw t chw cs flm cl1 note: refer to restraints for details on pulse-width restraints. 180 t chw (ns) 180 t clw t fs ?1000 (ns) t chw : cs high-level width t clw : cs low-level width figure 3 &6 &6 (input)
HD66520T 1021 block diagram v4r, v3r, v2r, v1r dispoff lcd drive circuit data latch circuit (2) data latch circuit (1) frc control circuit ram 160 240 2 bits i/o selector data line decoder address management circuit bidirectional buffer line counter we oe cs flm db7 to db0 a15 to a0 ls1, ls0 shl word line decoder y160 y1 y2 y3 cl1 m v4l, v3l v2l, v1l timing control circuit figure 4 block diagram
HD66520T 1022 address management circuit: converts the addresses input via a15Ca0 from the system to the addresses for a memory map of the on-chip ram. when several lsis (hd66520s) are used, only the lsi whose address space, set by pins ls0, ls1, and shl, contains the input address, accepts the access from the system, and enables the inside. the address management circuit enables configuration of the lcd display system with memory addresses not affected by the connection direction, and reduces burdens of software and hardware in the system. refer to the how to use the ls1 and ls0 pins to set pins ls0, ls1, and shl. timing control circuit: this circuit controls arbitration between display access and draw access. specifically, it controls access timing while receiving signals flm, cl1, &6 , :( , and 2( as input. flm and cl1 are used to perform refresh (display access), that is, to transfer line data to the liquid crystal circuit. &6 , :( , and 2( are used for the cpu to perform draw operation (draw access), that is, to read and write display data from and to the internal ram. this circuit also generates a timing signal for the frc control circuit to implement four-level grayscale display. line counter: operates refresh functions. when flm is high, the counter clears the count value and generates an address to select the first line in the ram section. the counter increments its value whenever cl1 is valid and generates an address to select subsequent lines in the ram section. bidirectional buffer: controls the transfer direction of the display data according to signals from pins :( and 2( in draw operation from the system. word line decoder: decodes duty addresses (a15 to a7) and selects one of 240 lines in the display ram section, and activates one-line memory cells in the display ram section. data line decoder: decodes pin addresses (a6 to a0) and selects a data line in the display ram section for the 7-bit memory cells in one-line memory cells activated by the word line decoder. i/o selector: reads and writes 8-bit display data for the memory cells in the ram section. display ram: 160 240 2-bit memory cell array. since the memory is static, display data can be held without refresh operation during power supply. frc circuit: implements frc (frame rate control) function for four-level grayscale display. for details, refer to half tone display. data latch circuit (1): latches 160-pixel grayscale display data processed by the frc control circuit after being read from the display ram section by refresh operation. this circuit is needed to arbitrate between display access for performing liquid crystal display and draw access from the cpu. data latch circuit (2): this circuit again outputs the data in data latch circuit (1) synchronously with signal cl1. lcd drive circuit: selects one of lcd select/deselect power levels v4r to v1r and v4l to v1l according to the grayscale display data, ac signal m, and display-off signal ',632)) . the circuit is configured with 160 circuits each generating lcd voltage to turn on/off the display.
HD66520T 1023 configuration of display data bit packed pixel method for grayscale display, multiple bits are needed for one pixel. in the hd66520, two bits are assigned to one pixel, enabling a four-level grayscale display. one address (eight bits) specifies four pixels, and pixel bits 0 and 1 are managed as consecutive bits. when grayscale display data is manipulated in bit units, one memory access is sufficient, which enables smooth high-speed data rewriting. the bit data to input to pin db7, db5, db3, and db1 becomes msb and the bit data to input via pin db6, db4, db2, and db0 is lsb. 0 0 1 0 2 1 3 0 4 0 5 1 6 1 7 1 bit physical memory 0123 0 0 1 0 2 0 3 0 4 0 5 1 6 0 7 1 0022 0 1 1 0 2 1 3 0 4 1 5 1 6 1 7 1 1133 frc control circuit grayscale level lcd display state 4 pixels/address address: n address: n + 1 address: n + 2 note: black is shown when the lcd select high-level power supply v1 (m = 1) and lcd select low-level power v2 (m = 0) are selected. white is shown when the lcd non-select high-level power supply v3 (m = 1) and lcd non-select low-level power supply v4 (m = 0) are selected. figure 5 packed pixel system
HD66520T 1024 half tone display (frc: frame rate control function) the hd66520 incorporates an frc function to display four-level grayscale half tone. the frc function utilizes liquid crystal characteristics whose brightness is changed by an effective value of applied voltage. different voltages are applied to each frame and half brightness is expressed in addition to display on/off. since the hd66520 has two-bit grayscale data per one pixel, it can display four-level grayscale and improve user interface (figure 6). figure 7 shows the relationships between voltage patterns applied to each frame, the effective voltage value, and brightness obtained. b) display with four values edit edit a) display with two values figure 6 example of user interface improvement
HD66520T 1025 white (0, 0) effective voltage light gray (0, 1) (vrm0) dark gray (1, 0) (vrm1) black (1, 1) (vrm2) (vrm3) v1 (m = 1) v2 (m = 0) v3 (m = 1) v4 (m = 0) white light gray dark gray black vrm0 vrm1 vrm2 vrm3 effective voltage brightness effective voltage and brightness 3rd frame 2nd frame 1st frame applied voltage pattern note: black is shown when the lcd select high-level power supply v1 (m = 1) and lcd select low-level power v2 (m = 0) are selected. white is shown when the lcd non-select high-level power supply v3 (m = 1) and lcd non-select low-level power supply v4 (m = 0) are selected. figure 7 effective voltage values vs. brightness
HD66520T 1026 address management the hd66520 has an address management function that corresponds to three display sizes all of which are standard sizes for portable information devices: a 160-dot-wide by 240-dot-long display (small information devices); a 320-dot-wide by 240-dot-long display (quarter vga s ize); and a 320-dot-wide by 480-dot-long display (half vga s ize). up to four hd66520s can be connected to at a time to configure easily liquid crystal displays with the resolutions mentioned above. driver layout and address management the y lines on a liquid crystal panel and memory data in a driver are inverted horizontally depending on the connection side of the liquid crystal panel and the driver. when several drivers are connected, address management is needed for each driver. although reinverted bit-map plotting or address management by the &6 pin in each driver are possible by using special write addressing, the load on the software is significantly increased. to avoid this, the hd66520 provides memory addresses independent of connection side, but responds to the setting of pins ls0, ls1, and shl. how to use the ls1 and ls0 pins pins ls1 and ls0 set the lsi position (up to four) as shown in figure 8 by assigning id numbers 0 to 3 to each hd66520. hd66520 hd66520 id = 0 id = 2 hd66520 hd66520 id = 1 id = 3 hd66503 hd66503 480 lcd panel 320 ls1 l l h h l: low level h: high level ls0 l h l h id no. 0 1 2 3 address arrangement upper-left side lower-left side upper-right side lower-right side figure 8 ls0 and ls1 pin setting and internal memory map
HD66520T 1027 how to use the shl pin it is possible to invert the relationship between the addresses and output pins y1 to y160 by setting the shl pin (figure 9). the upper left section on the screen can be assigned to address h0000 regardless of which side of the lcd panel the hd66520 is connected to. the relationship between the data bus and output pins the 8-bit data on the data bus has a 2-bit/pixel configuration for a 4-level grayscale display. in addition, the 8-bit data on the data bus has a relationship as shown in table regardless of the relationship between pins ls0, ls1, and shl. table 1 data bus and output pins data bus output pins db 0, 1 y1 y5 y153 y157 db 2, 3 y2 y6 y154 y158 db 4, 5 y3 y7 y155 y159 db 6, 7 y4 y8 y156 y160 hd66520 hd66520 y1 hd66520 hd66520 hd66503 hd66503 480 lcd panel y160 y1 y160 y160 y1 y160 y1 hd66520 hd66520 y1 hd66520 hd66520 hd66503 hd66503 480 lcd panel y160 y1 y160 y160 y1 y160 y1 when the hd66520 is connected to the back of the panel (shl = low). when the hd66520 is connected to the front of the panel (shl = high). 320 320 figure 9 address assignment and shl pin setting
HD66520T 1028 since the relationship between data bus pins db0 to db7 and the output pins are fixed, connect the data from the cpu to data bus pins db0 to db7 according to the driver arrangement on the panel as shown in figure 10. y160 y1 hd66520 liquid crystal panel y1 y160 hd66520 liquid crystal panel d0 db0 cpu data hd66520 data bus pin d1 db1 d2 db2 d3 db3 d4 db4 d5 db5 d6 db6 d7 db7 d0 db6 cpu data hd66520 data bus pin d1 db7 d2 db4 d3 db5 d4 db2 d5 db3 d6 db0 d7 db1 drive arrangement data bus connection when y1 is placed on the left side of the liquid crystal panel when y160 is placed on the left side of the liquid crystal panel figure 10 relationship between data bus pins db0 to db7 and output pins
HD66520T 1029 application example the hd66520 is suitable for a 160-dot-wide by 240-dot-long display (small information devices); a 320- dot-wide by 240-dot-long display (quarter vga s ize); and a 320-dot-wide by 480-dot-long display (half vga s ize). all of these are standard sizes for portable information devices. the following shows the system configuration. 240 240 line scan direction 160 160 hd66503 hd66520 small-size information device 160-dot-wide by 240-dot-long 160 hd66503 hd66520 quarter vga size 320-dot-wide by 240-dot-long 240 240 160 320 hd66520 160 hd66520 half vga size 320-dot-wide by 480-dot-long 480 160 320 hd66520 160 160 hd66520 hd66520 expands horizontally expands horizontally and vertically line scan direction hd66503 240 line scan direction hd66503 240 line scan direction figure 11 application examples
HD66520T 1030 small information device (shl = low) y1 y160 hd66520 liquid crystal panel scan direction 160 240 240 160 id no. 0 ls0 = low ls1 = low hd66503 0000 0001 0026 0027 0080 0081 00a6 00a7 0100 0101 0126 0127 7680 7681 76a6 76a7 7700 7701 7726 7727 7780 7781 77a6 77a7 l1 l2 l3 l238 l239 y1 y5 y153 y157 y4 y8 y156 y160 l240 d0 db0 cpu hd66520 d1 db1 d2 db2 d3 db3 d4 db4 d5 db5 d6 db6 d7 db7 y1 y2 y3 y4 y5 y6 y7 y8 y157 y158 y159 y160 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 0 0 1 1 0 0 1 0 1 1 0 0 1 1 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 0 0 1 0 1 1 0 0 1 1 0 1 0 0 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 0 0 1 0 1 1 0 1 0 0 1 0 1 1 0 1 1 1 1 0 0 0 0 display memory liquid crystal display image duty direction figure 12 small information device (1)
HD66520T 1031 small information device (shl = high) y160 y1 hd66520 160 240 240 160 id no. 0 ls0 = low ls1 = low hd66503 0000 0001 0026 0027 0080 0081 00a6 00a7 0100 0101 0126 0127 7680 7681 76a6 76a7 7700 7701 7726 7727 7780 7781 77a6 77a7 l1 l2 l3 l238 l239 l240 d1 db7 cpu hd66520 d0 db6 d3 db5 d2 db4 d5 db3 d4 db2 d7 db1 d6 db0 y160 y159 y158 y157 y156 y155 y154 y153 y4 y3 y2 y1 y153 y156 y160 y157 y5 y8 y1 y4 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 0 0 1 0 1 1 0 1 0 0 1 0 1 1 0 0 0 0 0 1 1 1 1 0 0 0 0 1 0 0 1 0 1 1 0 0 1 1 0 1 0 0 1 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 0 0 1 1 0 0 1 0 1 1 0 0 0 0 0 0 0 0 0 0 1 1 0 liquid crystal panel scan direction display memory liquid crystal display image duty direction figure 13 small information device (2)
HD66520T 1032 quarter vga size (shl = low) hd66520 160 320 id no. 0 ls0 = low ls1 = low hd66503 0000 0001 0026 0027 0080 0081 00a6 00a7 0100 0101 0126 0127 7680 7681 76a6 76a7 7700 7701 7726 7727 7780 7781 77a6 77a7 l1 l2 l3 l238 l239 y5 y153 y157 y8 y156 y160 l240 y1 y4 0028 0029 004e 004f 00a8 00a9 00ce 00of 0128 0129 014e 014f 76a8 76a9 76ce 76cf 7728 7729 774e 774f 77a8 77a9 77ce 77cf l1 l2 l3 l238 l239 y5 y153 y8 y156 l240 y1 y4 hd66520 160 240 240 y1 y160 y160 y1 ls0 = low ls1 = high id no. 2 y160 y157 liquid crystal panel scan direction figure 14 quarter vga size (1)
HD66520T 1033 d0 db0 cpu d1 db1 d2 db2 d3 db3 d4 db4 d5 db5 d6 db6 d7 db7 y1 y2 y3 y4 y157 y158 y159 y160 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 0 0 1 1 0 0 1 0 1 1 0 0 1 1 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 0 0 1 0 1 1 0 1 0 0 1 0 1 1 0 1 1 1 1 0 0 0 0 y157 y158 y159 y160 1 1 1 1 1 1 1 1 1 0 0 1 1 0 0 1 0 1 1 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 0 0 1 0 1 1 0 1 0 0 1 0 1 1 0 1 1 1 1 0 0 0 0 y1 y2 y3 y4 1 1 1 1 1 1 1 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 0 0 0 1 1 1 1 0 1 1 1 0 0 0 0 1 1 1 1 1 0 0 0 0 hd66520 hd66520 display memory liquid crystal display image duty direction display memory figure 15 quarter vga size (2)
HD66520T 1034 quarter vga size (shl = high) hd66520 160 id no. 0 ls0 = low ls1 = low hd66503 0000 0001 0026 0027 0080 0081 00a6 00a7 0100 0101 0126 0127 7680 7681 76a6 76a7 7700 7701 7726 7727 7780 7781 77a6 77a7 l1 l2 l3 l238 l239 l240 0028 0029 004e 004f 00a8 00a9 00ce 00cf 0128 0129 014e 014f 76a8 76a9 76ce 76cf 7728 7729 774e 774f 77a8 77a9 77ce 77cf l1 l2 l3 l238 l239 l240 hd66520 160 240 240 y1 y1 y160 y160 ls0 = low ls1 = high id no. 2 320 y153 y156 y160 y157 y5 y8 y153 y156 y1 y4 y5 y8 y160 y157 y1 y4 liquid crystal panel scan direction figure 16 quarter vga size (3)
HD66520T 1035 d1 db7 cpu d0 db6 d3 db5 d2 db4 d5 db3 d4 db2 d7 db1 d6 db0 y160 y159 y158 y157 y4 y3 y2 y1 1 1 1 1 1 1 1 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 0 0 1 1 0 0 1 0 1 1 0 0 1 1 0 0 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 0 1 1 1 1 y4 y3 y2 y1 1 1 1 1 1 1 1 1 1 0 0 1 1 0 0 1 0 1 1 0 0 1 1 0 0 0 0 0 0 0 0 0 y160 y159 y158 y157 1 1 1 1 1 1 1 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 1 0 0 1 0 1 1 0 0 1 1 0 1 0 0 1 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 0 0 1 0 1 1 0 0 1 1 0 1 0 0 1 0 0 0 0 1 1 1 1 hd66520 hd66520 display memory liquid crystal display image duty direction display memory figure 17 quarter vga size (4)
HD66520T 1036 half vga size (shl = low) hd66520 160 id no. 0 ls0 = low ls1 = low hd66503 0000 0001 0026 0027 0080 0081 00a6 00a7 0100 0101 0126 0127 7680 7681 76a6 76a7 7700 7701 7726 7727 7780 7781 77a6 77a7 l1 l2 l3 l238 l239 l240 0028 0029 004e 004f 00a8 00a9 00ce 00cf 0128 0129 014e 014f 76a8 76a9 76ce 76cf 7728 7729 774e 774f 77a8 77a9 77ce 77cf l1 l2 l3 l238 l239 l240 hd66520 160 240 480 y1 y160 y160 y1 ls0 = low ls1 = high id no. 2 hd66520 id no. 1 ls0 = high ls1 = low 7800 7801 7826 7827 7880 7881 78a6 78a7 7900 7901 7926 7927 ee80 ee81 eea6 eea7 ef00 ef01 ef26 ef27 ef80 ef81 efa6 efa7 l1 l2 l3 l238 l239 l240 7828 7829 784e 784f 78a8 78a9 78ce 78cf 7928 7929 794e 794f eea8 eea9 eece eecf ef28 ef29 ef4e ef4f efa8 efa9 efce efcf l1 l2 l3 l238 l239 l240 hd66520 y1 y1 y160 y160 ls0 = high ls1 = high id no. 3 y153 y156 y157 y160 y1 y4 y5 y8 y153 y156 y160 y157 y1 y4 y5 y8 240 160 160 y1 y5 y153 y157 y4 y8 y156 y160 y1 y5 y153 y157 y4 y8 y156 y160 hd66503 liquid crystal panel scan direction scan direction 320 figure 18 half vga size (1)
HD66520T 1037 d0 db0 cpu d1 db1 d2 db2 d3 db3 d4 db4 d5 db5 d6 db6 d7 db7 y1 y2 y3 y4 y157 y158 y159 y160 0 0 0 0 1 1 1 1 1 0 0 1 0 1 1 0 1 0 0 1 0 1 1 0 1 1 1 1 0 0 0 0 y157 y158 y159 y160 y1 y2 y3 y4 0 0 0 0 1 1 1 1 0 0 0 1 1 1 1 0 1 1 1 0 0 0 0 1 1 1 1 1 0 0 0 0 hd66520 hd66520 1 1 1 1 1 1 1 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 0 0 0 0 0 d6 db0 cpu d7 db1 d4 db2 d5 db3 d2 db4 d3 db5 d0 db6 d1 db7 y160 y159 y158 y157 hd66520 hd66520 1 1 1 1 0 0 0 0 1 0 0 1 0 1 1 0 0 1 1 0 1 0 0 1 0 0 0 0 1 1 1 1 y4 y3 y2 y1 y4 y3 y2 y1 y160 y159 y158 y157 1 1 1 1 1 1 1 1 1 0 0 1 1 0 0 1 0 1 1 0 0 1 1 0 0 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 0 0 1 1 0 0 1 0 1 1 0 0 1 1 0 0 0 0 0 0 0 0 0 liquid crystal display image duty direction display memory duty direction display memory display memory display memory figure 19 half vga size (2)
HD66520T 1038 half vga size (shl = high) hd66520 160 id no. 0 ls0 = low ls1 = low hd66503 0000 0001 0026 0027 0080 0081 00a6 00a7 0100 0101 0126 0127 7680 7681 76a6 76a7 7700 7701 7726 7727 7780 7781 77a6 77a7 l1 l2 l3 l238 l239 l240 0028 0029 004e 004f 00a8 00a9 00ce 00cf 0128 0129 014e 014f 76a8 76a9 76ce 76cf 7728 7729 774e 774f 77a8 77a9 77ce 77cf l1 l2 l3 l238 l239 l240 hd66520 160 240 480 y1 y1 y160 y160 ls0 = low ls1 = high id no. 2 id no. 1 ls0 = high ls1 = low 7800 7801 7826 7827 7880 7881 78a6 78a7 7900 7901 7926 7927 ee80 ee81 eea6 eea7 ef00 ef01 ef26 ef27 ef80 ef81 efa6 efa7 l1 l2 l3 l238 l239 l240 7828 7829 784e 784f 78a8 78a9 78ce 78cf 7928 7929 794e 794f eea8 eea9 eece eecf ef28 ef29 ef4e ef4f efa8 efa9 efce efcf l1 l2 l3 l238 l239 l240 y1 y160 y160 y1 ls0 = high ls1 = high id no. 3 320 240 160 160 y153 y156 y160 y157 y1 y4 y5 y8 y1 y5 y153 y157 y4 y8 y156 y160 y153 y156 y160 y157 y1 y4 y5 y8 y1 y5 y153 y157 y4 y8 y156 y160 hd66503 liquid crystal panel scan direction scan direction figure 20 half vga size (3)
HD66520T 1039 d1 db7 cpu d0 db6 d3 db5 d2 db4 d5 db3 d4 db2 d7 db1 d6 db0 y1 y2 y3 y4 y157 y158 y159 y160 0 0 0 0 1 1 1 1 1 0 0 1 0 1 1 0 1 0 0 1 0 1 1 0 1 1 1 1 0 0 0 0 y157 y158 y159 y160 y1 y2 y3 y4 0 0 0 0 1 1 1 1 0 0 0 1 1 1 1 0 1 1 1 0 0 0 0 1 1 1 1 1 0 0 0 0 hd66520 hd66520 1 1 1 1 1 1 1 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 0 0 0 0 0 d7 db7 cpu d6 db6 d5 db5 d4 db4 d3 db3 d2 db2 d1 db1 d0 db0 y160 y159 y158 y157 1 1 1 1 0 0 0 0 1 0 0 1 0 1 1 0 0 1 1 0 1 0 0 1 0 0 0 0 1 1 1 1 y4 y3 y2 y1 y4 y3 y2 y1 y160 y159 y158 y157 1 1 1 1 1 1 1 1 1 0 0 1 1 0 0 1 0 1 1 0 0 1 1 0 0 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 0 0 1 1 0 0 1 0 1 1 0 0 1 1 0 0 0 0 0 0 0 0 0 hd66520 hd66520 liquid crystal display image duty direction display memory display memory display memory display memory duty direction figure 21 half vga size (4)
HD66520T 1040 display-data transfer display ram data is transferred to 160-bit data latch circuits 1 and 2 at each falling edge of the cl1 clock pulse. since display data transfer and ram access to draw data are completely synchronous- separated in the lsi, there will be no draw data loss or display flickering due to display data transfer timing. the first line data transfer involves the first line marker (flm), which initializes a line counter, and transfers the first line data to data latch circuits 1 and 2. subsequent line data transfers involve transferring the second and the subsequent line data to data latch circuits 1 and 2 while incrementing the line counter value. first line data transfer the line counter is initialized synchronously with an flm signal. the first line is transferred to data latch circuits 1 and 2 at the falling edge of the cl1 (figure 22). subsequent line data transfer the second and the subsequent line data are transferred to data latch circuits 1 and 2 at the falling edge of the cl1 to update the line counter value (figure 23). cl1 flm line counter x + 1 1 2 xth + 1 line 1st line 2nd line 1st line xth line data latch circuit 1 data latch circuit 2 (y1 to y160) figure 22 first line data transfer cl1 line counter n + 1 n nth line nth + 1 line nth line nth ?1 line data latch circuit 1 data latch circuit 2 (y1 to y160) note: outputs y1 to y160 are converted into four levels before output according the liquid crystal altemating signal. figure 23 subsequent line data transfer
HD66520T 1041 draw access random cycle random cycle sequence is the same as that for the general-purpose sram interface (figures 24 and 25). it can easily be connected to a cpu address bus and data bus. a15 to 0 cs oe we db7 to 0 out db7 to 0 in valid dout figure 24 read cycle a15 to 0 cs oe we db7 to 0 out db7 to 0 in valid din figure 25 write cycle
HD66520T 1042 burst cycle continuous access (burst cycle) can be performed by enabling addresses and 2( or :( when &6 is low (figures 26 and 27). refer to restraints for the period of continuous transfer. a15 to 0 cs oe we db7 to 0 out db7 to 0 in valid dout valid dout valid dout figure 26 burst read cycle a15 to 0 cs oe we db7 to 0 out db7 to 0 in valid din valid din valid din figure 27 burst write cycle
HD66520T 1043 arbitration control the hd66520 controls the arbitration between draw access and display access. the draw access reads and writes display data of the display memory incorporated in the hd66520. the display access outputs display memory line data to the liquid crystal panel. in this case, draw access is performed before display access, so continuous access is enabled without having the system to wait. for arbitration control, draw access is recognized as valid when signal &6 is low. the following describes the typical examples of display memory access state during arbitration control. sequence line data transfer display access performed by subsequent line data transfer if no draw access is attempted, normal display access is performed when signal cl1 is low (figure 28). draw access 1 if draw access is attempted when signal cl1 is high, draw access is performed regardless of the display access (figure 29). cs nth + 1 line data display access nth line data display access cl1 display memory access state figure 28 sequence line data transfer draw access nth + 1 line data display access nth line data display access draw access cs cl1 display memory access state figure 29 draw access (1)
HD66520T 1044 draw access 2 if draw access is attempted when signal cl1 is low, the display access is suspended to perform draw access (figure 30). after the draw access, the display access is performed again. as a result, even if draw access is attempted asynchronously, at least one of the display accesses will be performed. display access by first line data transfer if no draw access is attempted, display access for the first line is performed when signal flm is high and cl1 is low. the display access for the second line is performed when signal cl1 is low (figure 31). draw access nth + 1 line data display access nth line data display access draw access nth line data display access cs cl1 display memory access state figure 30 draw access (2) 1st line data display access cs flm cl1 display memory access state 2nd line data display access figure 31 first line data transfer
HD66520T 1045 draw access 3 if draw access is attempted when signal flm is high, stop the display access is suspended to perform the draw access (figure 32). after the draw access, the display access is performed again. as a result, even if draw access is attempted asynchronously, at least one of the two display accesses will be performed. note: in order to satisfy draw access 3 and transfer the first line data, there are restraints for the period when pins flm and cl1 are both high and for the low level pulse width of pin &6 . refer to restraints for details on the restraints for the pulse width. 1st line data display access cs flm cl1 display memory access state 2nd line data display access 1st line data display access draw access draw access figure 32 draw access (3)
HD66520T 1046 example of system configuration figure 33 shows a system configuration for a 320-dot-wide by 240-dot-long lcd panel using hd66520s and common driver hd66503 with internal liquid crystal display timing control circuits. all required functions can be prepared for liquid crystal display with just three chips except for liquid crystal display power supply circuit functions. 160 hd66503 scan driver 240 160 320 power supply circuit hd66520 (id no.2) ls0 ls1 shl ls0 ls1 shl hd66520 (id no.0) doc (dispoff) flm, cl1, m / 3 / 1 v cc 1/240 duty cs, we, oe db0?b7 a15?0 3 / 8 / 16 / line scan direction cr r c figure 33 system configuration
HD66520T 1047 restraints the hd66520 can perform continuous draw access (burst access) when signal &6 is low. as a result, display data can be rewritten at high speed. however, since signal &6 is necessary to perform arbitration control between draw access and display access to the display memory, the following restraints exist for the pulse width of signal &6 . v cc = 3.0 to 4.5v read operation item symbol min max unit chip select high level width t chr 180 ns chip select low level width t clr 240 t fs C 1000 ns write operation item symbol min max unit chip select high level width t chw 180 ns chip select low level width t clw 180 t fs C 1000 ns v cc = 4.5 to 5.5v read operation item symbol min max unit chip select high level width t chr 120 ns chip select low level width t clr 180 t fs C 1000 ns write operation item symbol min max unit chip select high level width t chw 120 ns chip select low level width t clw 120 t fs C 1000 ns
HD66520T 1048 chip select high level width display access is performed when signal &6 is high during normal draw access. therefore, only the minimum display access time is necessary for the chip select high level width (figure 34). display access cs cl1 display memory access state draw access draw access t chr (t chw ) figure 34 chip select high level width
HD66520T 1049 chip select low level width when continuous draw access (burst access) is performed when signal &6 is low, the maximum display access time, that is, t fs C1000 (ns) is necessary for the chip select low level width (figure 35). this is needed to secure the display access period for the first line. when common driver hd66503 is used together with the hd66520, t fs can be calculated with the following formula. t fs = 4? duty ? flm 1 f flm : frame frequency n duty : duty when write operation is performed with the burst access having a frame frequency of 70 hz and a duty cycle of 1/240, display data of 77 bytes can be consequtively written in one burst access (write cycle is 180 ns). cs flm cl1 display memory access state 1st line data display access draw access t clr (t clw ) t fs 12 2nd line data display access 2nd line data access figure 35 chip select low level width
HD66520T 1050 absolute maximum ratings item symbol ratings unit notes power voltage logic circuit v cc C0.3 to +7.0 v 1 lcd drive circuit v ee v cc C 30.0 to v cc + 0.3 v input voltage (1) vt1 C0.3 to v cc + 0.3 v 1, 2 input voltage (2) vt2 v ee C 0.3 to v cc + 0.3 v 1, 3 operating temperature t opr C20 to +75 c storage temperature t stg C40 to +125 c notes: 1. the reference point is gnd (0v). 2. applies to pins ls0, ls1, shl, flm, cl1, m, a0 to a15, db0 to db7, ',632)) , &6 , :( , and 2( . 3. applies to pins v1l, v1r, v2l, v2r, v3l, v3r, v4l, v4r. 4. if the lsi is used beyond its absolute maximum rating, it may be permanently damaged. it should always be used within the limits of its electrical characteristics in order to prevent malfunction or unreliability.
HD66520T 1051 electrical characteristics dc characteristics 1 (v cc = 3.0 to 5.5v, gnd = 0v, v cc Cv ee = 8 to 28v, ta = C20 to +75c) item symbol applicable pins min typ max unit measurement condition notes input leakage current (1) i il1 except for db0 to db7 C2.5 2.5 a vin = v cc to gnd input leakage current (2) i il2 v1l/r, v2l/r, v3l/r, v4l/r C25 25 a vin = v cc to v ee tri-state leakage current i ist db0 to db7 C10 10 a vin = v cc to gnd vi-yj on resistance r on y1 to y160 1.0 2.0 k w i on = 100 a 1 note: 1. indicates the resistance between one pin from y1 to y160 and another pin from v1l/v1r, v2l/v2r, v3l/v3r, v4l/v4r when load current is applied to the y pin; defined under the following conditions: v cc Cv ee = 28v v1l/v1r, v3l/v3r = v cc C 2/10 (v cc Cv ee ) v4l/v4r, v2l/v2r = v ee + 2/10 (v cc Cv ee ) v1l/v1r and v3l/v3r should be near the v cc level, and v2l/v2r and v4l/v4r should be near the v ee level. all voltage must be within ?v. ?v is the range within which r on , the lcd drive circuits output impedance, is stable. note that ?v depends on power supply voltage v cc Cv ee . v cc v1l/r v3l/r v4l/r v2l/r v ee 6.4 2.5 828 relationship between driver output waveform and output voltage v cc ? ee (v) d v d v d v (v)
HD66520T 1052 dc characteristics 2 (v cc = 3.0 to 4.5v, gnd = 0v, v cc Cv ee = 8 to 28v, ta = C20 to +75c) item symbol applicable pins min typ max unit measurement condition notes input high level voltage (1) vih1 ls0C1, shl, flm, cl1, m, 0.8 v cc v cc v input low level voltage (1) vil1 ',632)) 0 0.2 v cc v input high level voltage (2) vih2 db0 to db7, cs, a0 to a15, 0.7 v cc v cc v input low level voltage (2) vil2 :(2( 0 0.15 v cc v output high level voltage voh db0 to db7 0.9 v cc v i oh = C50 a output low level voltage vol 0.1 v cc vi ol = 50 a current consumption during ram access i cc measurement pin v cc 8 10 ma access time 600 ns v cc = 3.3v 2 current consumption in lcd drive part i ee measurement pin v ee 200 300 a v cc Cv ee = 28v v cc = 3.3v t cyc = 59.5 s 2, 3 current consumption during display operation i dis measurement pin gnd 4060 a no access notes: 2. input and output currents are excluded. when a cmos input is floating, excess current flows from the power supply through to the input circuit. to avoid this, vih and vil must be held to v cc and gnd levels, respectively. 3. indicates the current when the memory access is stopped and the still image of a zig-zag pattern is displayed in its place.
HD66520T 1053 dc characteristics 3 (v cc = 4.5 to 5.5v, gnd = 0v, v cc Cv ee = 8 to 28v, ta = C20 to +75c) item symbol applicable pins min typ max unit measurement condition notes input high level voltage (1) vih1 ls0C1, shl, flm, cl1, m, 0.8 v cc v cc v input low level voltage (1) vil1 ',632)) 0 0.2 v cc v input high level voltage (2) vih2 db0 to db7, &6 , a0 to a15, 2.2 v cc v input low level voltage (2) vil2 :(2( 0 0.8 v output high level voltage voh db0 to db7 2.4 v i oh = C100 a output low level voltage vol 0.4 v i ol = 100 a current consumption during ram access i cc measurement pin v cc 13 16 ma access time 600 ns v cc = 5.5v 2 current consumption in lcd drive part i ee measurement pin v ee 200 300 a v cc Cv ee = 28v, v cc = 5.5v, t cyc = 59.5 s, no access 2, 3 current consumption during display operation i dis gnd 60 100 a notes: 2. input and output currents are excluded. when a cmos input is floating, excess current flows from the power supply through to the input circuit. to avoid this, vih and vil must be held to v cc and gnd levels, respectively. 3. indicates the current when the memory access is stopped and the still image of a zig-zag pattern is displayed in its place.
HD66520T 1054 ac characteristics 1 (v cc = 3.0 to 5.5v, gnd = 0v, v cc Cv ee = 8 to 28v, ta = C20 to +75c) display-data transfer timing no. item symbol applicable pins min max unit notes (1) clock cycle time t cyc cl1 10 s 1 (2) cl1 high-level width t cwh cl1 1.0 s (3) cl1 low-level width t cwl cl1 1.0 s (4) cl1 rise time t r cl1 50 ns (5) cl1 fall time t f cl1 50 ns (6) flm setup time t fs flm, cl1 2.0 s (7) flm hold time t fh flm, cl1 1.0 s notes: 1. 0.8 v cc (7) t fh 0.2 v cc (4) t r (5) t f 0.8 v cc cl1 flm (6) t fs (2) t cwh (3) t cwl (1) t cyc f cyc = 1/t cyc max: 100 khz when executing draw access with burst transfer, the period described in the restrains must be satisfied in the relationship with the arbitration control.
HD66520T 1055 ac characteristics 2 (v cc = 3.0 to 4.5v, gnd = 0v, v cc Cv ee = 8 to 28v, ta = C20 to +75c) draw access timing ? read cycle measurement conditions: input level: vih = 2.4v, vil = 0.8v output level: voh/vol = 1.5v output load: 1 ttl gate + 100 pf capacitor no. item symbol min max unit note (8) read cycle time t rc 240 ns (9) address access time t aa 240 ns (10) chip select access time t ca 240 ns (11) &6 high level width t chr 180 ns (12) &6 low level width t clr 240 t fs C1000 ns (13) 2( delay time t oe 150 ns (14) 2( delay time (low impedance) t olz 5ns (15) output-disable delay time t ohz 035ns (16) output hold time t oh 5ns ? write cycle measurement conditions: input level: vih = 2.4v, vil = 0.8v no. item symbol min max unit note (17) write cycle time t wc 180 ns (18) address-to- :( setup time t asw 30 ns (19) &6 high level width t chw 180 ns (20) &6 low level width t clw 180 t fs C1000 ns (21) address-to- :( hold time t ahw 0 ns (22) &6 -to- :( hold time t ch 0 ns (23) :( low level width t wlw 100 ns (24) :( high level width t whw 30 ns (25) data-to- :( setup time t ds 80 ns (26) data-to- :( hold time t dh 30 ns
HD66520T 1056 ac characteristics 3 (v cc = 4.5 to 5.5v, gnd = 0v, v cc Cv ee = 8 to 28v, ta = C20 to +75c) access timing ? read cycle regulation terms: input level: vih = 2.4v, vil = 0.8v output judge-level: voh/vol = 1.5v output load: 1 ttl gate + capa. 100 pf no. item symbol min max unit note (8) read cycle time t rc 180 ns (9) address access time t aa 180 ns (10) chip select access time t ca 180 ns (11) &6 high level width t chr 120 ns (12) &6 low level width t clr 180 t fs C1000 ns (13) 2( delay time t oe 100 ns (14) 2( delay time (low impedance) t olz 5 ns (15) output-disable delay time t ohz 035 ns (16) output hold time t oh 5 ns ? write cycle regulation terms: input level: vih = 2.4v, vil = 0.8v no. item symbol min max unit note (17) write cycle time t wc 120 ns (18) address-to- :( setup time t asw 20 ns (19) &6 high level width t chw 120 ns (20) &6 low level width t clw 120 t fs C1000 ns (21) address-to- :( hold time t ahw 0 ns (22) &6 -to- :( hold time t ch 0 ns (23) :( low level width t wlw 80 ns (24) :( high level width t whw 30 ns (25) data-to- :( setup time t ds 60 ns (26) data-to- :( hold time t dh 20 ns
HD66520T 1057 (9) t aa oe we cs address i/o out (8) t rc (14) t olz (16) t oh (15) t ohz valid data oe (10) t ca we cs address db out (11) t chr (14) t olz (16) t oh (15) t ohz valid data (13) t oe (13) t oe (9) t aa (12) t clr read cycle 2 read cycle 1
HD66520T 1058 (23) t wlw (18) t asw oe we cs address i/o in (17) t wc (26) t dh (24) t whw (25) t ds (23) t wlw (21) t ahw oe we cs address i/o in (17) t wc (26) t dh (24) t whw (18) t asw (25) t ds (22) t ch (19) t chw (20) t clw valid data valid data write cycle 2 write cycle 1

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